QFN and SON assembly: thermal pads, printing, and joint verification

QFN and SON connections are mainly underneath the component. Center pads can serve electrical, thermal, and mechanical roles and require more than treatment as larger ground pads. Balance perimeter and center solder volumes: excessive center paste can lift the package and impair perimeter connections, while insufficient paste or solder drainage through vias can weaken underside connections. Acceptable edge appearance alone does not establish center-connection suitability.

First determine exactly what the center pad connects to

Start with the full part number's datasheet and package drawing, confirming perimeter pins, exposed center pad, pin-one features, and electrical requirements. Different center pads may not permit the same potential; similar outlines do not justify old library reuse. Check PCB copper pads, solder mask, thermal vias, and finish, identifying open, filled, or otherwise treated holes. Drawn copper area is not necessarily an actual flat solderable surface.

TI SLUA271C discusses QFN/SON lands, stencils, and assembly, emphasizing experimental process optimization. It is application guidance; review component-specific recommendations first. One guide dimension set cannot cover all QFNs, and thermal conclusions for one stackup do not transfer directly to different copper weights and cooling structures.

How to calculate area ratio and cutout coverage

Rectangular aperture area ratio is L×W÷[2×(L＋W)×T], where L/W are aperture length/width and T is stencil thickness, all in the same units. Aspect ratio is W÷T. Example: L＝0.80 mm, W＝0.23 mm, T＝0.125 mm gives area ratio 0.184÷0.2575≈0.715 and aspect ratio 1.84. Both help assess release and stencil fabrication but do not automatically establish acceptable printing.

For low area ratios, SLUA271C discusses release approaches such as electroformed nickel; the stencil supplier and trial printing still need confirmation. Widening apertures also increases solder volume and bridging risk, while thinner stencils affect other components. Review the board's smallest apertures and high-volume locations together, using a product-appropriate stencil structure if needed.

Center window example: a 3×3 mm pad has 9 mm² area; four 1.1×1.1 mm windows total 4.84 mm², approximately 53.8% nominal coverage. At 0.125 mm stencil thickness, geometric volume is 0.605 mm³. This is geometry only: printed paste area does not equal effective post-reflow connection area because release, melting, and volatilization change the result.

Selecting center aperture and via treatment together

TI discusses approximately 50% to 70% center-pad paste coverage as a typical starting point, warning that a fully printed solid area can cause floating. This is process guidance, not an acceptance criterion for every component. Verify window dimensions, spacing, hole locations, and actual standoff together. Check volume/distribution using trial printing or SPI before examining reflow results.

Open center vias can drain solder; adding paste alone may create perimeter bridges or package lift. Confirm PCB hole treatment matches the design, and test surface flatness, stencil windows, and thermal processing together. Address obvious board unevenness or paste-distribution errors before attempting to compensate for everything with the reflow profile.

A void percentage alone cannot determine acceptance

Assess center connections using void location, shape, connected channels, soldered area, and the actual thermal path. TI's high-power and JEDEC reference-board discussions have specific objects and conditions; they are not universal industry acceptance limits. Set order limits from component requirements, product thermal design, reliability targets, and approved specifications, defining imaging and calculation methods.

How temperature measurement and inspection cover bottom-side risks

Measure temperature profiles on actual boards and joints, meeting both paste requirements and the most sensitive component's limits. Record thermocouple attachment, locations, board configuration, and tooling. Center thermal pads and small perimeter pads behave differently; one top-of-package measurement cannot establish that all joints entered the window. Manage moisture status and rework thermal exposure too.

X-ray shows structure in specified underside regions; electrical and functional tests verify related nets and operation. These are complementary. Visible side fillets also depend on end-face construction and plating; do not require identical side appearance on every QFN. For visual inspection or AOI, specify covered areas and conclusions requiring other methods.

Recording sequence from prototype to approved solution

Engineering example: a power board's first reflow produces center voids and a few perimeter opens. Link print volume, placement, and imaging to the same board. If excessive center volume lifts the component, verify windowing before increasing temperature. Once printing is stable, compare thermal processes within the shared allowable window. Retain temperature-rise and functional results under matching loads/environments for each group, keeping unchanged controls so multiple adjustments are not conflated.

• Inputs: full part number, package drawing, PCB pads/hole structure, materials, and product thermal requirements
• First article: stencil revision, print volume, placement, and measured profile
• After soldering: imaging scope, calculation definitions, perimeter connections, and issue photos
• Operating verification: load, environment, firmware, power dissipation, or related temperature rise
• Outputs: approved window, criteria sources, uncovered limitations, and change-triggered reinspection conditions

Rework changes local thermal history and surfaces; do not copy original first-article records directly to reworked items. Record removal/reinstallation, cleaning, material replacement, and reinspection, assessing nearby components where needed. Passing prototypes supports the current configuration, not automatically other QFN models or board revisions. For the complete-board route, combine with Assembly Scope Confirm, see detection records Factory Verification.

QFN and SON supplementary issues

What matters when cleaning beneath a low-standoff package?

Check flux/cleaner compatibility, residue removability, and drying. A clean-looking surface does not establish absence of underside residue; validate the method against product requirements.

Can the center pad use thermal adhesive instead of solder?

Follow the specific component's electrical and thermal requirements; do not independently replace a required soldered center connection with adhesive. Material choice also involves potential, standoff, and reliability and requires product review.

How to maintain comparability between imaging and thermal testing

Void statistics must define whether the denominator is center-pad projection, actual soldered area, or another area, recording overlap and thresholds. Algorithms can yield different percentages; compare only matching definitions. Hold dissipation, environment, airflow, and mounting constant during thermal tests, or temperature differences may reflect system conditions. Link aperture revisions, SPI volume, profiles, and imaging to board identification before observing thermal/electrical behavior. Before destructive analysis such as microsections, retain nondestructive records and identify sampling locations. Production monitoring follows confirmed sensitive factors; reevaluate after material, hole-treatment, or thermal-structure changes. One successful window pattern does not cover every power level and thickness. State whether samples were reworked: solder volume and residue may differ, so do not combine reworked and original-process samples into one average and claim improvement. Retain separate conclusions for center and perimeter connections too.