Reflow compatibility does not establish permission for package bodies to contact a solder wave. Wave, selective soldering, dip simulation, and hot-air reflow have different thermal histories and heated regions. For mixed assembly, confirm permitted exposure by part number before choosing direct passage, shielding, later installation, or a different through-hole soldering route. Package appearance alone cannot group all SMT parts.
Why not just compare maximum temperature
TI SCEA041 compares wave soldering, dipping, and standard reflow on particular SOIC samples, noting that rapid dip-sample heating is not equivalent to actual wave/reflow exposure and examining moisture and wave duration. This 2008 experimental study supports thermal-history/method boundaries; its temperatures, times, and results do not approve every modern package.
The same peak can involve very different ramp rates, preheating, and body contact. Reflow classification does not automatically establish package-body wave immersion capability. Identify whether heat contacts leads, joints, or plastic bodies first, then check specific component/package documentation. Without compatibility evidence, retain pending status rather than assuming acceptance.
Convert BOM into thermal exposure grouping table
| Grouping | Basis | Process Output |
|---|---|---|
| Pass allowed under approved conditions | Clear restrictions for part numbers or packages | Preheat, Contact conditions and orientation |
| To mask | Sensitive areas cannot touch directly | Masking map, fixture, and actual measurement verification |
| Requires post-installation or post-soldering | Thermal limits or process interference | Post-assembly sequence, operations, and inspection |
| Insufficient Documentation | Missing applicable statement or condition conflict | Review supplementary evidence, testing, or substitution routes |
Group not only ICs but connector plastics, sensors, crystals, switches, adhesives, markings, and other sensitive parts. Location affects exposure; top components and bottom contact regions need different descriptions. After double-sided SMT, through-hole soldering also requires review of existing joints, heavy-part retention, bow, and flux entering hidden areas.
How to compare wave, selective and secondary soldering
| Route | Favorable Conditions | Critical Trade-offs and Verification |
|---|---|---|
| Whole-board wave soldering | Through-hole assembly suitable for the route and layout | Bottom components, shielding, thermal exposure, and solder contact |
| Selective soldering | Requires local treatment and nozzle access | Neighbor spacing, programs, preheating, and local thermal effects |
| Controlled post-soldering | Small quantities of special parts or components unsuitable for pre-installation | Operational consistency, access, labor time, and reinspection |
| Adjust design or assembly sequence | Existing layout causes thermal or tool conflicts | Document revision and full route re-confirmation |
Selective soldering does not eliminate thermal-sensitivity review; heat still travels through leads, copper, and board structures. Manual secondary soldering also needs a process window with specified tools, methods, and inspection. Compare carrier fabrication, changeovers, maintenance, and testing labor alongside soldering costs per joint.
Which actual functions of the shielding fixture need verification
Carriers must address shielding, contact openings, location, underside clearance, and drainage, beyond simply blocking SMT regions. Small openings can restrict solder access; excessive thickness changes heat input; clamps/supports can stress thin boards. Materials, heat resistance, and maintenance must match actual conditions; distortion or residue can alter the next lot's results.
Record carrier revision and loading during temperature measurement. Profiles measured without carriers do not establish identical conditions after installation. Measuring only through-hole joints may miss rapid heating of nearby SMT bodies. Trials should also check wave contact, component retention, and cleaning access, then retest affected functions after the final operation.
Estimate contact time, then verify it by measurement
Engineering example: an effective contact zone 40 mm long in the travel direction at 20 mm/s gives ideal geometric contact time 40÷20＝2 seconds. This is not a component allowance; actual wave shape, angle, immersion, dual waves, and carriers change contact. Confirm thermal history with suitable methods, then compare current component/process limits.
Record preheating, each contact, and repeated exposures separately; adding all seconds into one total is insufficient. For two contacts, spacing and cooling affect temperature; rework or another pass is an additional process. Check moisture-sensitive parts' previous opening, storage, and treatment histories too. Compare related records with MSL and reflow conditions.
How to locate anomalies after secondary thermal process
If a board passes after reflow but fails after through-hole soldering, preserve both inspection stages and identify newly introduced differences. Check heated regions, shielding, component placement/retention, flux/cleaner residue, supply, and firmware before deciding on material analysis. No visible package cracks does not exclude internal effects, and not every failure is caused by wave temperature.
Method scenario: a board with a sensitive sensor and large connector is planned for full-board wave soldering after reflow. No documentation supports sensor-body wave contact, so compare shielding with later installation. Shielding trials must check sensor thermal history and connector-joint formation; later installation must establish workable handling, cleaning, and calibration. Choose by complete-route verification, not by which method sounds more advanced.
Inputs and outputs from first article to mass production
- Input the controlled BOM, top/bottom layouts, full part numbers, and permitted-exposure documents
- Map contact, shielding, later-installation, and tool-access regions; identify carrier revision
- Confirm temperature/contact in the actual configuration, retaining conveyor and program conditions
- Compare through-hole joints, SMT appearance, bow, and affected electrical/function results
- Approve operation sequence, monitoring points, carrier checks, and anomaly-quarantine scope
Final records should distinguish material/component declarations, engineering experiments, and approved production conditions. Passing experimental samples does not establish compatibility for every part number. Reconfirm affected items after carrier, component, or program changes. For preliminary inquiries with only a board and BOM, identify risk components before formal route review. For detailed deliverables, see Mixed assembly scope and Detection and Re-verification.
Common Thermal Exposure Questions
Does adhesive on underside parts permit wave soldering?
Adhesive can retain parts but does not change package-body thermal limits. Confirm adhesive material, curing, solder contact, and component compatibility.
Can one manual solder dip replace wave verification?
Not automatically. Demonstrate that preheating, contact, and thermal history match verification objectives. SCEA041's specific experiments show that methods can create different thermal shocks.
Distinguish study samples from current component permissions
Retain sample package, method, and study date when citing experiments. Reliability-stressed report samples do not permit every SMT part to use those wave conditions; absence of one observed failure does not establish risk-free other structures. Obtain matching current-BOM documents, defining verification needs or avoiding exposure when evidence is missing. First articles should check solder access to target leads, shadowed regions, and carrier effects on venting/drainage. Tooling, wave state, or flux changes can alter results. Maintain process, carrier, and maintenance records to distinguish component limits, drift, and structural issues. Underside adhesives and curing also need process identification; completed retention is not thermal permission. If cleaning must precede sensitive-part installation, include post-installation joints, cleanliness, and functional reinspection in the route instead of ending records after shifting the protection issue to the final operation.
After line or shift changes, check that key conditions remain within approved limits and link them to this lot's execution records.
Source material and applicable scope
- Texas Instruments, “Wave Solder Exposure of SMT Packages”; SCEA041, 2008-09; checked on 2026-10-17; sections 1 Introduction, 2 Process Characterization, 3 Designed Experiment, and 4 Conclusions. Supports thermal-history differences and verification methods for specific SOIC experiments, not wave permission for all SMT components.
