An SMT package's assembly method cannot be determined from its outline name alone. Start with the full part number, package code, and manufacturer's drawing to connect PCB pads, solder mask, stencil, component feeding, placement orientation, and thermal processing. Even if a functionally equivalent replacement fits the old footprint, differences in bottom pads, lead length, heat-flow paths, or thermal limits may require a revision.
Identify the exact package before selecting application guidance
Texas Instruments' public SMT literature directory separates QFN, BGA, leaded packages, and general packaging thermal processes, with links covering moisture sensitivity, reflow, and wave soldering. This shows why package and process research should follow separate paths. The directory establishes document topics only; it does not provide pad dimensions or temperature criteria for every part. Continue with the specific device datasheet's package drawing, recommended land pattern, and limits, recording the applicable revision.
| Package Target | Priority Focus | Project Verification Items |
|---|---|---|
| Pin-visible package | Lead geometry, coplanarity, pads, and adjacent components | Printing, placement, solder-joint visibility, and rework |
| QFN and SON | Peripheral and center pads, vias, and solder volume | Paste release, floating risk, bottom connections, and thermal conditions |
| BGA | Ball map, ball pitch, pad definition, and warpage | Hidden connections, measured thermal profiles, and electrical test coverage |
| Special power or module package | Thermal pads, electrical connections, underside, and construction | Dedicated pads, support, cooling, and process restrictions |
Footprint-library names should distinguish parts with similar dimensions but different land patterns. Do not use only 'QFN32' to represent every 32-pin device. When reviewing drawings, confirm top and bottom views, the first-pin mark, pin numbering, dimension units, and tolerances. A 3D model helps check physical interference but does not establish that copper pads, solder mask, and stencil are correct; replacing the model does not mean the manufacturing library has been updated.
Pads, solder mask, and stencils perform different functions
Copper pads establish actual connections and routing relationships, solder mask affects solderable areas and isolation, and the stencil controls solder-paste distribution and volume. These three are usually related but cannot unconditionally share the same outline. A central thermal pad also requires consideration of electrical connection, thermal vias, and potential solder-drain paths. Confirm the use of non-solder-mask-defined or solder-mask-defined pads against device recommendations and PCB fabrication conditions.
Stencil thickness affects paste release and solder volume at every aperture. A board combining fine-pitch devices, large connectors, or central thermal pads may require tradeoffs with a single thickness, which must be reviewed together with the stencil design. Enlarging apertures alone does not solve paste-release issues, and reducing solder to eliminate bridging must not compromise reliable connections. For specific QFN and SON methods, continue reading Heat dissipation pads, cutouts, and solder joint verification.
Change checklist for package replacement
| Check layer | Comparison Content | Affected Outputs |
|---|---|---|
| Circuit and Part Number | Pin definitions, electrical conditions, suffixes, and functional differences | Schematic, BOM, and substitution approval |
| PCB Library | Pads, solder mask, thermal vias, keepouts, and dimensional tolerances | Footprint library, Gerber files, and fabrication drawings |
| Printing and Placement | Stencil, orientation, pickup, supply packaging, and adjacent components | Stencil, coordinates, and program |
| Thermal and Material | Moisture sensitivity, allowable profiles, alloy, and cleaning restrictions | Process card, temperature measurement, and material management |
| Inspection and Testing | Visibility, hidden solder joints, electrical checks, and function | Inspection procedures, fixtures, and first article records |
Change approval should include differences between old and new revisions, not just a new part number. Changing only supply packaging may affect feeding and machine programs; changing the package may require PCB and stencil changes; production changes under the same part number require assessment of assembly effects based on the change notice. Updating only one document at a time creates revision-mismatch risks. Retain the release list together with the effective lot.
Thermal processing must fit the shared window for materials and devices
Solder paste needs appropriate heating and time in the molten state, while devices, the PCB, and previously installed components each have thermal limits. Confirm the shared process window through temperature measurements on actual boards. Large copper regions, shields, heavy components, and carriers change hot-to-cold differences; double-sided reflow and subsequent through-hole soldering add thermal exposure. An example profile in a manufacturer's application report cannot replace first-article records for the current product.
Specify exact measurement locations and attachment methods, retaining board configuration, program, and equipment conditions. For sensitive devices, check allowable heating rates, exposure, and repeated processing as well as peak temperature. Local rework heating may affect neighboring packages, so the process route should state protection measures and retest scope. Passing one reflow does not mean the same device may directly contact wave solder. For the relevant limitations, see SMT component wave soldering thermal exposure.
Which first-article outputs establish that a footprint library is usable?
First compare actual first-article components with the approved BOM, then link printing, placement, and post-soldering results to the same reference designators. Verify volume and offset during printing, orientation and position during placement, and visible joints and targeted hidden areas after soldering. Finally, check function under specified electrical and thermal loads. Passing one stage establishes only that stage's result and does not eliminate subsequent validation.
- Library verification record: part number, package code, drawing revision, and pin numbering
- Manufacturing record: stencil revision, apertures, board support, and first-article printing results
- Temperature record: measurement locations, actual profile, device limits, and material process window
- Inspection record: reference designator, photographs or imaging, coverage, and criteria source
- Product results: firmware, load, interfaces, temperature rise or relevant performance, and anomaly resolution
Continue using this approved documentation in production; do not temporarily use an unreviewed package at a reference designator. First-article sample count and specific criteria depend on product risk and contract requirements. This page does not invent a universal pass rate or void percentage. Label the configuration of retained samples so they are not mistaken for the current revision years later.
Why does changing from QFP to QFN require more than a different pad outline?
Engineering scenario: a controller with similar functionality changes from a QFP with visible leads to a QFN with a center pad. Even with an unchanged software interface, recheck pin arrangement, center-pad potential, grounding and cooling, vias, and stencil. Optical inspection previously covered most leads; the revision adds bottom connections and requires a revised inspection plan. A poor center connection may cause temperature rise at high load or intermittent operation. Normal operation at first power-up is insufficient confirmation.
The appropriate output is a complete difference and validation table, not merely the phrase 'compatible replacement.' During prototyping, compare electrical and thermal performance under specified loads and inspect the post-soldering structure. If the new package saves area, also verify neighboring components and rework clearance. This is an example of an engineering method; it does not represent a completed customer project or any unconfirmed company package capability limit.
Common package data issues
Can an EDA tool's built-in footprint library be used directly for an order?
It still requires verification against the full part number and manufacturer's drawing. Library revisions, dimension systems, and land-pattern strategies may differ. A built-in library does not mean the current product has been reviewed.
Can different packages share one reflow profile?
Possibly, but demonstrate that every critical location on the actual board stays within the shared process window. Matching equipment program names do not establish validation.
Library audit must also cover manufacturing layers and coordinates
Do not review a footprint solely by its silkscreen outline. Check copper, solder mask, solder paste, courtyard, and origin, and confirm that the first pin after rotation matches the coordinate convention. Include component height and underside construction in assembly-clearance checks. For libraries copied from other projects, retain the source and modification differences so special stencil apertures from a previous product are not carried over without explanation. When feeding prototype results back into the library, distinguish design-error corrections from process adjustments for a specific route. Pad changes may affect routing and electrical clearances, whereas stencil changes do not necessarily require copper changes; do not treat both as indiscriminate scaling. After approval, archive the actual production files and revisions, and recheck subsequent manufacturing-data exports so an updated source library does not coexist with output from an old project. If documentation includes multiple package options, lock the selected code in the BOM and library, and check whether manufacturer drawing revisions change the recommended land pattern; a matching functional part designation alone does not rule out differences in package codes or material suffixes.
Source material and applicable scope
- Texas Instruments, SMT & packaging application notes; version: not specified on the directory webpage; checked 2026-10-17; sections: QFN, BGA, Leaded packages, and General packaging information; scope: directs research to the relevant package and process literature, without providing complete manufacturing limits for a specific part number.
- Texas Instruments, QFN and SON PCB Attachment; version SLUA271C, revised 2023-12; checked 2026-10-17; sections 3 to 5; scope: methods for jointly evaluating QFN/SON pads, stencils, and assembly.
Confirm process based on actual boards · Define first article and inspection delivery
Worked package-to-manufacturing-file cross-check
Teaching example, not a KFPCBA customer build or approved footprint. Suppose designator U7 calls for Texas Instruments TPS62130RGTR. TI identifies its RGT package as a 16-pin, 3 × 3 mm VQFN with an exposed thermal pad. The data sheet's package drawing and pin table are the device-side sources; the fictional board exports below are deliberately incomplete so the release decision is visible.
| Check | Manufacturer source | Illustrative project packet | Result and next action |
|---|---|---|---|
| Part and drawing identity | TPS62130 data sheet, SLVSAG7F; RGT package drawing RGT0016C. Confirm the current drawing revision at release. | BOM says TPS62130RGTR; EDA library name is only RGT16-3x3-v4. | Part number matches, but a library name does not prove pad geometry. Compare the actual copper, mask and paste exports with the selected drawing. |
| Pin 1 and placement | TI's top view places pin 1 at the marked corner and labels it SW. | CPL lists U7 at X 32.4 mm, Y 18.7 mm, rotation 90°; the export convention and first-pin mark were omitted. | Unconfirmed. Overlay the board image and actual feeder orientation; record the machine convention before programming. |
| Exposed pad connection | TI requires the exposed pad to connect to AGND, PGND and the common ground plane and be soldered. | Gerber shows a center copper area, but the exported net assignment and via treatment were not supplied. | Hold. Reconcile schematic net, copper, mask openings, vias and paste pattern with the design owner. |
| Stencil revision | TI's QFN/SON attachment note treats peripheral and center-pad apertures separately; its examples are not a replacement for a part-specific release. | PCB export is rev B while stencil file is rev A. | Hold. Compare aperture locations and paste volume against rev B copper and the actual printing process; issue a matched stencil revision. |
| Inspection coverage | Bottom connections are not fully visible to ordinary optical inspection. | First-article plan lists visual inspection only; no agreed hidden-joint or electrical coverage is recorded. | Define applicable imaging, electrical and functional checks and their limits with the buyer before the build. |
A usable release record attaches the full part number, manufacturer drawing revision, approved library/export versions, stencil and CPL revision, orientation overlay, and first-article results. In this example the decision remains hold. Continue to the QFN/SON assembly review for package-specific joint and stencil questions, or use the SMT service input checklist to prepare the manufacturing packet.
Source boundary for the worked record
TI TPS62130 family data sheet, revision F and RGT0016C package drawing; checked 2026-11-11. Supports the selected example component and package connection checks only; the fictional board exports, release holds and KFPCBA capability are not validated by this document. Read the primary source.
