BGA joints are beneath the component; release requires more than edge appearance or one startup. Begin with ball maps and nets, linking pad definitions, printing, thermal processes, and inspection coverage to specific balls. X-ray, electrical testing, and function each supply partial evidence; identify remaining blind spots even when combined. The generic BGA label does not determine pitch, thermal windows, or rework conditions.
Establish ball-to-network correspondence first
Use the full part number's datasheet and drawing to confirm ball count, depopulated locations, first-ball orientation, pitch, and alloy, then compare schematic nets and PCB libraries. Keep top views, bottom views, and manufacturing coordinates distinct. Power, ground, reserved, or test balls may not be individually assessed by ordinary startup, so inspection plans must identify each target ball's function.
| Ball Grid Category | Required Inputs | Evidence for scheduling |
|---|---|---|
| Power and Ground | Parallel relationships, current paths, and measurement points | Short circuit, voltage drop, and load-related checks |
| Memory and high-speed signals | Network, interface, timing, and program | Connection inspection and specified stress testing |
| Low-Speed Control and Startup | Pull-up, status pins, and startup conditions | Boundary conditions or interface test cases |
| Retained and Unreachable Solder Balls | Component definition and design handling | Identify directly untestable areas and alternative evidence |
Ball tables also support fault location. If logs show only “memory failure,” list related data, address, power, and clock nets before deciding whether connections are suspect. Do not attribute every startup problem to BGA soldering; firmware, supply, reset, and peripheral conditions can also fail.
SMD and NSMD are not interchangeable labels
Here, SMD means solder-mask-defined pads, where a smaller mask opening limits the copper area; NSMD means non-solder-mask-defined pads, with openings larger than copper pads so copper mainly defines the soldering boundary. TI AN-1126 explains both and manufacturing considerations. Select against current package recommendations, PCB tolerances, fanout, and reliability targets; one approach does not automatically suit every pitch.
Also check solder-mask dams, pad surfaces, vias, and fanout. For via-in-pad, filling and finishing affect flatness and connections; improper fanout/openings can change the effective soldering area. AN-1126 is a 2004 application report for PBGA and related packages. This article uses its pad/process analysis methods, not its old alloy temperatures, MSL, or reliability figures as modern component limits.
Printing, warpage, and temperature must be observed jointly
Verify paste volume, offset, and release across regions, retaining distributions at corners, centers, and large copper areas. Components and PCBs may deform differently during heating; room-temperature flatness does not guarantee reflow contact. Supports and carriers must account for bow, underside parts, and heat distribution; flattening alone must not introduce new contact or temperature problems.
Measure actual configured boards, retaining thermocouple locations/attachment, programs, and equipment conditions. Paste, ball material, component, and PCB limits need a shared window. Record rework counts, moisture histories, and local heating. Current manufacturer documents define component thermal limits; one profile from an old report cannot cover all BGAs.
Complementary checks required for hidden connections
| Method | Primary Contribution | Cannot be proven independently |
|---|---|---|
| Optical or Edge Inspection | Direction, location, and partial appearance | All bottom ball connection quality |
| X-ray Imaging | Clues for bridges, missing balls, and some structural anomalies | All metallurgical interfaces and functions are normal |
| Electrical connection check | Open/short and parameters for reachable networks | Uncovered ball locations and stability under all operating conditions |
| Functional and Stress Test Cases | Behavior under specified loads, interfaces, and durations | Unpowered state and long-term life |
Record component reference designator, board identification, view, method, and criteria for imaging. Two-dimensional overlap can conceal interface problems; select other angles, tomography, or further analysis for the target defect where needed. Parallel power/ground balls can hide a single-ball fault from simple continuity, while functional tests may never exercise the affected net. State these limits in coverage tables rather than hiding them under “inspection normal.”
Narrow intermittent failures to testable hypotheses
Preserve failed boards as found, recording supply, firmware, temperature, load, interfaces, and reproduction frequency. Changes after heating or pressing are only clues, not sole evidence of a BGA connection fault; these actions can change contact, bow, and other components. Avoid repeatedly reheating until operation returns and delivering the board without traceable root cause or damage history.
Compare net tests, imaging, and actual profiles for suspect balls. For failures at certain panel positions, check support and heat distribution; for one component lot, review material and moisture history. If firmware changes remove the symptom, verify whether they merely bypass the problem. Agree on samples and methods before disassembly, dye analysis, microsectioning, or other work, retaining pre-destructive records.
Engineering example: failed memory stress testing
Suppose a prototype starts normally but reports intermittent errors under a specified memory stress case. This is not a Historical Production Example. Freeze firmware and test conditions, check consistency in error addresses/channels, then examine supply, timing, termination, and layout. Inspect target balls on related BGA nets, use imaging for structural clues, and check first-article printing and hot/cold locations. An observed corner-connection anomaly then supports further assessment of warpage, solder volume, or local thermal processing.
After rework, rerun the original failing case, related interfaces, and affected supply loads in addition to startup, preserving old failures and new results. Record new lots for replaced parts; limit pilot conclusions to new PCB/process revisions where changed. Product risk and approved plans determine per-board imaging, sampling, or other combinations; this page gives no universal sampling percentage.
First article and rework delivery document list
- Full component part number, ball map/net mapping, and PCB pad/hole-structure revision
- Identities and records for materials, moisture status, stencil, printing, and placement
- Measured profiles, board supports/tooling, limit sources, and approved windows
- Objects, coverage, criteria, and raw results for imaging, electrical, and functional tests
- Rework reasons, reference designators, thermal processes, material changes, and reinspection conclusions
Distinguish observed, tested, and uncovered items for later lot reuse. For assembly scope, see Board fabrication route See test criteria for Inspection and Factory Records Moisture sensitivity history can be combined MSL Management Organize.
BGA validation supplementary questions
Can passing whole-board function eliminate hidden-connection inspection?
It depends on product risk and the approved plan. Function establishes only executed cases; agree on structural checks before pilot production instead of deleting inspections after seeing results.
Is a removed and reballed component equivalent to a new one?
No. Check manufacturer permission, thermal history, ball material, processing, and verification boundaries, recording whether reuse is permitted in the current product.
Decide handling and re-inspection boundaries before rework
Before BGA rework, confirm replaceability, board surfaces, nearby components, and thermal history. Preserve failure/imaging evidence before removal so cleaning does not erase original interfaces. Avoid copper/mask damage during pad cleaning, and record replacement sources, moisture status, and ball materials. Component/product requirements determine whether reballing or reuse is permitted. Record controlled processes, materials, actual thermal histories, and inspection rather than merely “resoldered once.” Final reinspection covers original failures and affected nets, including nearby areas where necessary. One working interface does not establish that other heated parts are unaffected. Boards with unknown histories or repeated rework require approved disposition, not repeated heating until incidental startup followed by delivery. Identify rework-tooling revisions and supported packages. Changes to nozzle dimensions, bottom preheating, or support require assessment of heat distribution and bow; operator familiarity alone must not determine settings.
Source material and applicable scope
- Texas Instruments, “AN-1126 BGA (Ball Grid Array)”; SNOA021C, 2004-05; checked on 2026-10-17; sections 5 Design Recommendations and 6 Assembly Recommendations. Supports pad definitions, assembly, and inspection methods. Old-package example temperatures and reliability figures are not guarantees for current components.
Worked ball-to-net coverage record for first-article review
Fictional teaching example, not a component map or KFPCBA test result. Replace every coordinate and net with the selected manufacturer's ball map, approved schematic and actual board files. A passing functional test does not prove every hidden joint is sound.
| Ball / intended net | Accessible evidence | Selected check and observed example | Uncovered condition and action |
|---|---|---|---|
| A1 / VDD_IO | Rail test point TP12, shared with other loads | Power-up voltage in specified fixture range; record unit, rail load and meter ID | Rail reading cannot identify the integrity of A1 alone; obtain an approved hidden-joint method or retain explicit risk approval. |
| B3 / RESET_N | TP17 and reset timing log | Assert and release reset under the agreed supply ramp; retain waveform ID | Room-temperature pass does not cover vibration or thermal intermittency; decide whether stress testing is in scope. |
| C5 / DATA_2 | No isolated probe point | Interface loopback in the approved firmware image; record version and error count | Loopback may mask a marginal joint. If structural imaging is ordered, record the regions and limitations; otherwise mark this ball unverified. |
| D6 / NC | Manufacturer map required | No electrical test assumed | Confirm that the actual device calls this ball NC. Do not invent a net or infer acceptance from silence. |
Attach the manufacturer ball-map revision, schematic/netlist export, board and fixture revisions, sample identity, method, acceptance criterion, observed result, image or log ID and disposition owner. Separate unobserved from failed; an unavailable inspection method is not a pass. Rework requires a new unit history and defined post-rework coverage.
ADI's BGA package and PCB design guidance explains why pad, stencil and assembly decisions must use the actual device requirements. It does not validate this fictional ball map or guarantee inspection coverage. Agree the deliverable in PCB assembly testing before quoting.
Source boundary for the worked record
Analog Devices, Ball Grid Array Packages and PCB Design Guidelines; checked 2026-11-11. Supports device-dependent board and assembly planning only; it does not validate the fictional ball map, any measured joint result or available KFPCBA inspection coverage. Read the primary source.
