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PCB Stackups

PCB stackup: align electrical and lamination structures

Stackup tables support layout, impedance solving, and production. Each layer needs its function, finished copper weight, and adjacent dielectrics; dielectric layers need core/PP models and dielectric thicknesses after lamination, rather than only total board thickness. Submit preliminary drafts for factory review before routing.

Structural ItemContent to FillInspection Purpose
Signal/reference layerLayer-by-layer functions, critical nets, and continuous reference planesMaintain return-path continuity and identify layer transitions
Copper layerBase copper and target finished copper thickness, copper distributionDistinguish outer plating and check copper balance
Dielectric LayerModel, glass style/resin, and target finished thicknessConstrain lamination and the impedance model
Via Layer PairThrough holes, blind vias, buried vias, and backdrill stop layersMap lamination/drilling operations
Impedance GroupTrace geometry, W/S, reference layers, targets, and tolerancesCorresponding test coupons and TDR acceptance

How to compare two candidate stackups

Compare reference-plane continuity and interlayer connections first, then calculate routing margin, total thickness, and hole aspect ratios. Compare costs using the material specifications, lamination count, and testing requirements. Reducing layer count while adding HDI build-up cycles does not necessarily reduce total cost. Symmetry checks must consider dielectric thickness, copper weight, and actual copper distribution together.

Changes after version confirmation

Material substitutions, dielectric-thickness adjustments, copper-weight changes, and via layer-pair changes can affect impedance and fabrication. Re-solve affected nets for each new stackup; after compensation approval, update Gerber/impedance tables so production files and design models use the same revision.

Inputs and outputs

Inputs include layer functions, board thickness, material candidates, copper weight, hole tables, and electrical constraints. Outputs are the approved stackup, via layer-pair diagram, impedance groups, permitted compensation range, and first-article verification requirements.

Multi-Layer Routing, HDI build-up structures, Impedance Acceptance, Material Review, Submit stack-up draft

Engineering reference | Digital PCB stackups: material databases and controlled manufacturing structures: methodological reference; third-party design methods or material documentation do not represent KFPCBA manufacturing capabilities.

Six-layer stack-up example: determine layer function first

Six-layer PCB layer-function and dielectric reference diagram
layersExample FunctionManufacturing and electrical notes
L1SignalCritical traces reference the adjacent L2 ground plane
L2Ground PlaneMaintain continuous return paths and check splits and vias
L3SignalCorrespond to approved reference plane and adjacent dielectric thickness
L4Power PlaneAllocate core copper thickness by load and plane distribution
L5Ground PlaneProvide a continuous reference plane for adjacent signal layers
L6SignalReference the L5 ground plane and account for port transitions

The diagram is not to scale and specifies no layer copper weights or dielectric thicknesses. Add core/PP models, dielectric thicknesses after lamination, and base/finished copper to the formal stackup; determine layer functions for four-, eight-, twelve-, and sixteen-layer boards according to nets, routing, and hole structures.

What else should the stackup table sent to the factory include

DocumentationRequired Content
Materials and copper layersComplete grades, core/PP, and base/finished copper for every layer
Via Layer PairThrough holes/blind vias/buried vias, start/end layers, and fabrication sequence
Impedance GroupNets/trace geometry, targets, tolerances, and corresponding reference planes
Approval BoundaryCompensation permissions, substitution rules, revisions, and first-article inspections

Compare multi-layer board types → Compare HDI build-up structures →

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