Engineering Selection Reference
Ethernet PCB: six-layer 100Ω fabrication review
Six-layer 100Ω Ethernet fabrication requires review against current drawings. For bare interface boards, distinguish MDI from digital-side nets and provide magnetic-component, shield-ground, and isolation-gap drawings. Continuous return paths must respect isolation boundaries. Deliver netlists, slot dimensions, and net-specific impedance records; the 100Ω reference does not establish complete-system certification.
For Ethernet PCBs, first define bare-board prototyping or production scope. Please provide Gerber data, drill files, board outline, and layer stackup, materials/processes, quantity, and manufacturing acceptance requirements. Six layers separate MAC/PHY digital domains from magnetic-component ports, prioritizing 100Ω nets
Six-layer 100Ω Ethernet review starts with six-layer MDI 100Ω differential nets; quotation documentation also needs MDI nets, magnetic components, and isolation gaps. Subsequent specification and manufacturing-input tables link design targets to inspection methods.
Why choose this structure for Ethernet interface boards
Ethernet boards need clear boundaries between MAC/PHY digital domains, magnetic components, and external ports; six layers can provide reference planes for each critical trace group. This product uses 100Ω MDI differential as a reference target for industrial network interfaces and Gigabit controller mainboards.
Which costs are included in six-layer Ethernet PCB quotations?
Quotes include six-layer FR4 materials/fabrication, magnetic-component isolation regions and slot profiling, MDI target nets, and coupon tests. Port continuity, PHY functions, and system isolation/EMC verification are different deliverables, not one 100Ω test charge. Align MDI net counts, connector drawings, and isolation boundaries before comparing quantities and area meaningfully.
Quotation terms depend on the approved files, quantity, material supply, tests and delivery requirements.
Prepare a structured RFQ or use the short inquiry form.
Enter the following items in one itemized quotation: specify cost units and tax/shipping basis, with separate columns for first orders and same-revision repeat orders. The table is a procurement breakdown method, not a ready-made price list; reference specifications require approval against current fabrication drawings.
| Quotation items and pricing boundaries | Actual inputs requiring alignment for this model | Repurchase of same version and change boundaries |
|---|---|---|
| Materials/fabrication, quoted per batch or accepted board | Isola 370HR FR4; 6 layers; inner copper 35µm; outer base copper 18µm/finished target 35µm | Recurs on repeat orders; material, layer-order, or copper-weight changes require requotation |
| Holes and forming, per approved hole table | Ø0.30mm through holes; ground-return vias beside differential layer transitions | Reorders follow the same revision; review operations before Ethernet-net changes |
| Surface finish/packaging, noting areas and batches | ENIG; no arbitrary copper additions in magnetic-component isolation regions | Incurred by actual batch; confirm packaging, storage conditions, and surface-finish substitutions separately |
| Engineering/tooling preparation, identifying one-time or per-batch charges | Ethernet nets: distinguish PHY-side and magnetic-component-side differential nets; provide magnetic-component/interface layouts and target data rate. | Verify file revisions, ownership, and storage condition before reusing old tooling; do not assume reuse is free |
| Structural/special inspections, identifying coupons, hole groups, or samples | Map coupons individually to target pairs; complete-board communication requires separate post-assembly testing. Record slot widths/boundaries and netlist revisions to avoid incorrectly merging shield ground with signal ground. | List initial prototype validation and per-batch sampling separately; quote per-board requirements separately rather than assuming everything is completed once |
| Delivery scope, listing reports and pass quantity | Ethernet bare PCB, isolation-domain/shield-ground drawings, target nets, and impedance reports; magnetic-component port test structures supplied as needed. | Retain revision links and batch records on repeat orders; list component assembly, firmware, and complete-unit testing separately |
Can Ethernet PCBs and USB controlled-impedance boards share a design?
Both may have differential nets, but this Ethernet board handles PHY digital domains, magnetic components, and external-port isolation, while USB boards focus on connector and ESD transitions. Changing USB90Ω to 100Ω does not complete Ethernet layout. Compare four versus six layers by whether isolation regions and digital reference planes can coexist.
| Comparison Dimension | Ethernet impedance PCB fabrication | USB impedance PCB prototyping |
|---|---|---|
| Material and Grade | Isola 370HR FR4 | Isola 370HR FR4 |
| Layer Count and Structure | 6 Layer | 4 Layer |
| Hole Structure and Dimensions | Ø0.30mm through holes; ground-return vias beside differential layer transitions | Ø0.25mm through holes; keep USB pairs on the same layer where possible |
| Application | Gigabit Ethernet controllers; industrial network interfaces | USB data adapters; portable acquisition equipment interfaces |
How are layer count and 100Ω targets determined for Gigabit Ethernet boards?
Identify MDI-side and digital-side nets by PHY model, then allocate signals and reference planes. 100Ω is an MDI starting point; chip documentation defines digital-side rules. Shield ground must not cross isolation domains merely to create continuous copper. Check component positions and copper keepouts before selecting layers and coupon layer pairs.
| Decision Sequence | This Model Input | Generated Auditable Output |
|---|---|---|
| 1 define usage and boundaries first | Distinguish PHY-side and magnetic-component-side differential nets; provide magnetic-component/interface layouts and target data rate. | Map coupons individually to target pairs; complete-board communication requires separate post-assembly testing. |
| 2 fixed conditions affecting structure | Provide shield grounding, isolation gaps, and copper keepouts to define slot fabrication and electrical-test net partitioning. | Record slot widths/boundaries and netlist revisions to avoid incorrectly merging shield ground with signal ground. |
| 3 Align Networks with Manufacturing Targets | 100Ω differential MDI reference target; TDR+separate port continuity/network performance tests | Provide target nets, layer pairs, and verification scope; review with Ø0.30mm through holes and ground-return vias beside differential layer transitions |
| 4 then verify quotation and release | Isola 370HR FR4; 1.60mm reference target; ENIG; no arbitrary copper additions in magnetic-component isolation regions | Request quotations using material/pattern/inspection lists at the same revision; list unapproved substitutions as separate alternatives rather than including them in the baseline quotation |
Ethernet interface board manufacturing specifications
| Specification Items | Clarify Configuration/Target |
|---|---|
| Material and Grade | Isola 370HR FR4 |
| Layer Count and Structure | 6 Layer |
| Total Board Thickness | 1.60mm reference target |
| Dielectric thickness and interlayer relationship | Signal-to-reference-ground target 0.15mm; copper prohibited in transformer isolation domains |
| Base Copper and Finished Copper | Inner copper 35µm; outer base copper 18µm/finished target 35µm |
| Hole Structure and Dimensions | Ø0.30mm through holes; ground-return vias beside differential layer transitions |
| Trace Width and Spacing | 0.125/0.125mm reference design |
| Impedance target and measurement method | 100Ω differential MDI reference target; TDR+separate port continuity/network performance tests |
| Surface Finish | ENIG; no arbitrary copper additions in magnetic-component isolation regions |
| Application | Gigabit Ethernet controllers; industrial network interfaces |
| Deliverables | Ethernet bare PCB, isolation-domain/shield-ground drawings, target nets, and impedance reports; magnetic-component port test structures supplied as needed. |
Ethernet Interface Board Layer Stackup and Hole Structure
The following shows functional layer order/material structure for this reference configuration, not a production stackup drawing; do not infer thickness from graphic proportions. Match copper-layer numbering to via layer pairs item by item in approved fabrication files.
| Top to Bottom | Layer Responsibilities/Structure |
|---|---|
| L1 | PHY/Interfaces |
| L2 | Digital Ground |
| L3 | Digital Signals |
| L4 | Power |
| L5 | Reference Ground |
| L6 | Interface/Components |
Hole structure: Ø0.30mm through holes; ground-return vias beside differential layer transitions
Trade-off between continuous return path and isolated copper-free zones
More layers do not replace PHY layout requirements. Circuit design determines ground/shield relationships and isolation on both sides of transformers; do not place copper across isolation regions to create complete ground. Digital-chip and MDI-side interfaces may require different impedance/routing rules.
Differential-transition ground vias and shield-ground boundaries: manufacturing checks
Keep differential pairs symmetric around magnetic components; place transition ground vias only within regions permitted to connect. Clearly mark inner-layer copper keepouts at isolation boundaries, chassis-ground connections, and test points so manufacturing adjustments preserve interface boundaries.
Net-specific TDR and isolation netlists: acceptance items
Perform net-specific TDR alongside bare-board continuity testing. Actual PHY prototypes separately verify link speed, port stability, and system isolation/EMC conditions; do not describe a bare-board 100Ω report as complete Ethernet equipment certification.
Ethernet interface board delivery scope
Applications: Gigabit Ethernet controllers; industrial network interfaces.
Ethernet bare PCB, isolation-domain/shield-ground drawings, target nets, and impedance reports; magnetic-component port test structures supplied as needed.
MDI nets, magnetic components, and isolation gaps: quotation inputs
Submit MDI nets, magnetic components, and isolation gaps, converting tabled targets into inspectable drawings. The following inputs separately define artwork, material, or structural inspection scope; freeze quotation revisions with approved drawings.
| Inputs required to be completed for this product | Engineering Decisions Affected | Records/delivery as agreed in the order |
|---|---|---|
| Ethernet Network | Distinguish PHY-side and magnetic-component-side differential nets; provide magnetic-component/interface layouts and target data rate. | Map coupons individually to target pairs; complete-board communication requires separate post-assembly testing. |
| Isolation Boundary | Provide shield grounding, isolation gaps, and copper keepouts to define slot fabrication and electrical-test net partitioning. | Record slot widths/boundaries and netlist revisions to avoid incorrectly merging shield ground with signal ground. |
Ethernet controlled-impedance PCB fabrication: pricing, selection, and procurement FAQ
Which costs are included in six-layer Ethernet PCB quotations?
A project-specific quotation requires review of the available files, quantity, materials, requested tests, delivery destination, taxes, shipping, and trade terms. Add specified materials, processes, and inspections not yet included to the total cost. Standard board references do not cover every configuration of this product. Any formula on this page organizes cost inputs; it is not a quoted rate.View cost items, calculation conditions, and sources.
Can Ethernet PCBs and USB controlled-impedance boards share a design?
A USB board does not become Ethernet merely by changing 90Ω to 100Ω. Ethernet involves PHY digital domains, magnetic components, and port isolation; USB focuses on connector/ESD transitions. Component rules, return paths, and copper keepouts differ. View Specific Comparison Basis
How are layer count and 100Ω targets determined for Gigabit Ethernet boards?
Distinguish PHY digital-side and MDI magnetic-component-side nets first, then assign layer pairs and targets by component rules. 100Ω is the MDI starting point; other nets may differ. Adding copper across isolation regions for continuous ground violates boundaries, so one universal layout rule is inappropriate. View Specific Comparison Basis
Does an Ethernet bare-board quote include transformers and RJ45 connectors?
Bare-board quotes generally cover PCB fabrication; magnetic components, RJ45 soldering, and port performance belong to materials and assembly and should be itemized separately. For complete interface PCB assemblies, provide the BOM and port-testing requirements.
Can Ethernet isolation slots be removed to save cost?
Slots belong to the specific isolation design. Before removal, recheck electrical clearances, inner copper keepouts, and system requirements. Bare-board continuity acceptance cannot justify slot removal, and CAM must not add copper bridges independently.
Which records should I check when selecting an Ethernet PCB manufacturer?
Check target pairs against coupon layer pairs, isolation netlists, and slot dimensions, confirming shield ground is not merged with signal ground. For link results, review assembly verification with specified PHY and port conditions; bare-board reports do not include complete-system certification.
Can both sides of Ethernet magnetic components share one set of quoted inspection items?
List PHY-side and interface-side nets, shield ground, and isolation domains separately before defining coupon/electrical-test coverage. List gap dimensions and copper-keepout layers separately to prevent net merging. Communication-rate verification requires assembled components and port conditions and cannot be counted as completed bare-board electrical testing.
How are per-board and per-panel Ethernet controlled-impedance quotations converted?
Retain isolation slots, shield ground, and magnetic-component domains in panelization; mark interface/PHY-side coupons by target nets, and prevent process rails from bridging isolation. State deliverable boards per panel, purchased panels, and board/panel delivery condition. Divide actual panel fabrication charges by corresponding accepted board count; list setup, specialized inspections, and packaging separately, without promising yield from theoretical utilization.
How should first-order one-time charges and reorder costs be separated for Ethernet controlled-impedance fabrication?
First confirm Ethernet-net and isolation-boundary documentation, stating whether engineering, tooling, or test setup is charged once. Map coupons individually to target pairs; complete-board communication needs separate post-assembly tests. Verify files and ownership before tool reuse; current materials, fabrication, and approved inspections still incur costs. List renewed preparation after changes separately rather than relying on the old total.
Can I obtain an Ethernet controlled-impedance budget before net documentation is complete?
Describe application, outline, quantity, and available drawings for a budget identifying gaps. Formal review requires separate PHY-side/magnetic-component-side differential nets, magnetic-component/interface layouts, and target rate. Deliver coupons mapped individually to target pairs; complete-board communication needs separate post-assembly tests. Confirm fabrication/inspection quotes after conditions freeze. Initial inquiries need not include every file, but estimates do not cover undefined structures by default.
What must be reconfirmed when materials, hole tables, or installation conditions change on an Ethernet reorder?
Provide shield grounding, isolation gaps, and copper keepouts to define slot fabrication and electrical-test net partitioning. Record slot widths/boundaries and netlist revisions to avoid merging shield and signal ground. Map changes to previous material/hole-table/mechanical files item by item to determine drawing, process, or measurement updates; unchanged product name and layer count do not establish identical reorder conditions.
If two Ethernet quotes use the same material, which configurations still need comparison?
Check nets on both PHY/magnetic-component sides, coupons corresponding to 100Ω targets, and copper keepouts across all layers. Link pricing including RJ45/transformer assembly covers different deliverables from bare-board electrical-test pricing.
Which reports should link to board identifiers before Ethernet prototypes move to production?
Map coupons individually to target pairs; complete-board communication needs separate post-assembly tests. Record slot widths/boundaries and netlist revisions to avoid merging shield and signal ground. Link material lots, approved fabrication files, and results to current sample identifiers; production uses the revision with issues closed. Old coupon/artwork reports support comparison but cannot replace current inputs; define uncovered complete-system objects separately.
When small-batch Ethernet unit prices fall, how can I tell whether total procurement costs decreased?
Separate Ethernet bare boards from interface PCB assemblies including magnetic components/RJ45, adding communication and EMC verification by target. Identical 100Ω labels do not establish equal order scope. Add setup, fabrication, agreed inspections, packaging, and shipping, then divide by accepted delivery quantity for equal-scope totals and per-board allocation. Use current quotes for amounts and rates; assume no fixed discount.
Comparison of Ethernet interface board with adjacent board types
Current configuration distinction: six layers separate MAC/PHY digital domains from magnetic-component ports, prioritizing 100Ω nets
- Four-Layer 90 Ω USB Interface Board — Thin four-layer 90Ω differential board addressing impedance continuity at connectors/ESD components
- Eight-layer DDR and high-speed acquisition impedance board — Manages single-ended/differential nets together, focusing on timing topology and layer transitions rather than serial interfaces
Impedance PCB Complete Product Catalog · All PCB Products
Material and design basis for Ethernet interface board
- Engineering reference | Isola 370HR material: high Tg and frequency-dependent parameters: Published manufacturer material data
- Engineering reference | General high-speed interface layout: return paths, length, and layer transitions: Design methodology
When citing these resources, record material revisions and design conditions for six-layer MDI 100Ω differential nets; first articles focus on net-specific TDR and isolation netlists. After material, copper-weight, or hole-structure changes, update drawings and inspections before release.
Request Quote for This PCB Configuration: cite product ID 225, attach critical circuit/interface information and quantity, and list specifications to retain or adjust.
