TPS22918 is a 1–5.5 V single-channel load switch with configurable rise time and output discharge. It switches power domains but is not a limiter isolating every load fault. Slower rise reduces capacitor inrush but can affect downstream startup. Design CT, source capability, output capacitance, and load behavior jointly.
List downstream behavior during power-up first
Inputs include voltage, transient-current capability, harness impedance, effective output capacitance, startup current, minimum operating voltage, and reset requirements. Some loads draw before voltage settles and cannot be modeled as capacitance alone. Define ON power-up defaults; do not float it awaiting firmware.
The 2 A maximum continuous switch rating remains limited by drop/temperature. At 3.3 V, typical RON is about 53 mΩ; at 1 A, drop is about 53 mV and dissipation 53 mW. At 2 A, conduction loss is about 0.212 W. These are typical-condition estimates; recheck hot maximum resistance, supply, and package. Headline values are not arbitrary-board guarantees.
Estimate using CT relationship then measure actual slope
The manual approximates SR＝0.55×CT＋30, with CT in pF and SR in µs/V. Estimate rise time as VIN times SR using the manual's 10%–90% definition; it does not apply to CT＝0 pF. At CT＝1000 pF, SR is about 580 µs/V; at VIN＝3.3 V, estimated rise is 1.914 ms. This is a typical approximation; measure actual capacitors/loads.
Capacitor charging current is approximately IC＝C×dV/dt. Independently, a 220 µF load rising linearly from 0–3.3 V in 3 ms draws about 0.242 A, plus actual load current during that interval. Do not combine 10%–90% time with full voltage swing or ignore DC-bias-reduced capacitance.
| Design Selection | Yield | Mandatory Re-verification |
|---|---|---|
| Increase CT | Slow output rise time | Downstream reset, startup, and linear-region dissipation |
| Increase input energy storage | Mitigate partial input drop | Input power-on and upstream power capability |
| Adjust output capacitor | Change surge and local power supply | Load stability and application transients |
| Delay load startup | Separate charging and business power take | Control timing and default fault state |
QOD determines whether shutdown truly resets the load
QOD may connect to VOUT through an external resistor, directly to VOUT for internal discharge, or remain open per the manual to disable discharge. Choose by shutdown sequence, residual voltage, capacitance, and allowable discharge current. Do not always short it for fastest discharge or assume low ON means a fully unpowered load.
The discharge approximation V(t)＝V0exp(−t/RC) applies only to corresponding equivalent resistance/capacitance models. At an assumed 10 kΩ and 100 µF, the time constant is 1 s; decay from 3.3 V to 0.33 V takes about 2.303 s. Actual QOD resistance, parallel loads, and pin backfeeding change waveforms; measure threshold-crossing times.
Input power loss and external interfaces can create reverse paths
USB, signals, other domains, or stored charge can backpower downstream circuits. TPS22918 is not automatically a complete reverse blocker. Analyze VOUT/VIN relationships and body-diode paths per the manual. Rapid restarts may retain input/output voltage; include external-interface states in tests.
QOD discharge concurrent with external power can create extra current or prevent full shutdown. Map all supply/I/O paths, then separately verify interface insertion/removal, input-first power loss, and load-domain-first shutdown. Use suitable reverse-blocking/current-limiting structures when required, not CT adjustments as substitutes.
Ensure measurement covers real nodes before and after switching
Keep VIN, VOUT, and decoupling wide/short; isolate enable/CT loops from strong interference. Keep CT-to-ground compact and trace component tolerances/dielectrics. Provide short-ground probing near both input/output; upstream-entry measurements do not replace switch-pin voltages.
Hot steady-state drop, startup differential voltage, and rapid-switching energy are different tasks. One startup without reset validates only that source/load condition; low battery, cold capacitors, or repeated switching may differ. Cover actual allowed ranges and retain effective capacitance/harness revisions.
Synchronized waveforms are more useful than isolated voltages
| Scenario | Synchronized Observation | Output Conclusion |
|---|---|---|
| First Power-On | ON, VIN, VOUT, current, and downstream reset | Surge, drop, and effective startup moment |
| Application load | Output current, voltage, and fault logs | Conduction voltage drop and transient power supply |
| Shut-off | ON, output residual voltage, and I/O status | Discharge time and recharge path |
| Fast Restart | Different off intervals and residual voltage | Reset integrity and re-establishment |
Outputs should be enable–input–output timelines plus CT/QOD materials and load revisions, not just “switch normal.” If VIN drops first, inspect upstream supply/inrush. If VOUT stalls mid-ramp, inspect load startup. If residual voltage persists after ON falls, inspect discharge/backfeeding. Change one parameter at a time for valid comparisons.
Plot valid states of multiple domains on one timeline
For multidomain systems, list input, switched output, reset, and peripheral-I/O validity together. Communication driven from another domain before downstream power settles can cause backfeeding or indeterminate startup. Domain voltage curves reveal whether CT changes improve inrush but disrupt sequencing.
Power-up inputs include minimum voltage, maximum capacitance, and load-start timing. Shutdown inputs include stored energy, discharge paths, and external-interface states. Outputs are event times and valid windows per domain. Verify load-specified slew/sequence requirements directly; load-switch typical waveforms cannot replace them.
Distinguish rapid restart from cold startup after full discharge in repeated-switching tests. Brief off periods may retain registers/internal states, making apparent recovery different from reset. Observe reset, communication, and residual voltage, defining restart completion rather than merely renewed output rise.
Large-capacitance startup exposes switches to voltage difference and current simultaneously; steady-state averages do not cover that energy. Evaluate actual waveforms and repeated-start thermal states. Repeated startup failures should trigger supply/load-behavior review rather than indefinitely increasing CT.
Retain actual assembled CT/QOD values and tolerances at delivery. Control software-enable strategies and hardware defaults too, avoiding omitted debug-jumper states in production files.
Is the longest rise time always safest?
No. Loads may require bounded slew, domain sequencing, or timely reset-region crossing. Excessively slow rise changes startup dissipation. Define load needs first, then choose and measure slew; reduced inrush alone is insufficient acceptance.
Input capacitance cannot replace supply capability
Larger local input capacitors buffer some transients but still require upstream charging and may create plug-in inrush. Measure initial connection and subsequent load turn-on, not only switched-output waveforms. Retain source current-limit behavior and cable impedance with inputs.
If downstream circuits repeatedly restart at intermediate voltage, compare reset thresholds, load current, and VOUT rise. CT changes may only alter oscillation periods; solve supply capability and startup strategy together. Acceptance must show entry into and stable operation within the working range, not one peak.
Source material and applicable scope
- Texas Instruments, “TPS22918 5.5-V, 2-A, 52-mΩ On-Resistance Load Switch”; version Rev. C, 2017-07; checked 2026-10-17; relevant sections: Slew Rate Control, Quick Output Discharge, Application, Power Supply, Layout. Supports the 1–5.5 V load switch, CT approximation, and QOD connections, not current-limiting or reverse-blocking guarantees.
